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Total 6건
1 페이지
게시판 검색
2009
6
International
"A Novel Damage-Free High-k Etch Technique Using Neutral Beam Assisted Atomic Layer Etching (NBALE) for Sub-32nm Technology Node Low Power Metal Gate/High-k Dielectric CMOSFETs"
K.S.Min, C.Y.Kang, C.Park, C.S.Park, B.J.Park, J.B. Park, M.Hussain, J.C.Lee, B.H.Lee, P.Kirsch, H.H. Tseng, R.Jammy, G.Y.Yeom,
Proc. of Int. Elect. Dev. Meeting,
2009.
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5
International
"NEMS-CMOS hybrid technology and its applications"
B.H.Lee, C.H.Cho, H.J.Hwang, S.K. Lim, S.Y. Lee, H.Hwang,
NANO Korea,
2009, Invited.
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4
International
"Dipole model explaining high-k/metal gate field transistor threshold voltage tuning"
P.D.Kirsch, P.Sivasubramani, J. Huang, C.D.Young, M. A. Quevedo-Lopoez, H. C.Wen, H. Alshareef, K. choi, C.S.Park, K.Freeman, M.M.Hussain, G.Bersuker, H.R.Harris, P. Majhi, R.Choi, P. Lysaght, B.H.Lee, H.-H Tseng, R.Jammy, T. S. Boscke, D. J. Lichtenwalne,
Electrochem. Soc. Transaction, 19(1), p.269,
2009, Invited.
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3
International
"Dielectric Breakdown Characteristics of Stacked High-k Dielectrics"
B.H.Lee, R.Choi,
Electrochem. Soc. Transaction (ECS), San Francisco, 19(2), p.289,
2009, Invited.
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2
International
"Reliability characterization methods for MOSFETs with metal electrode/high-k dielectric stack"
B.H.Lee,
Proc. of ICICDT,
2009.
1
International
"Exploratory NEMS-CMOS Hybrid Devices for Post CMOS era"
B.H.Lee,
Proc. of ISTC, Electrochem. Soc. Transaction, 18(1), p.857,
2009, Invited.
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