포항공대 EESL Fearless challenge

Gate Postdoping to Decouple Implant/Anneal for Gate, Source/Drain, and Extension:Maximizing Polysilicon Gate Activation for 0.1 µm CMOS Technologies

Conference

Tech. Dig. of VLSI Symposium

Author

H. Park, D. Schepis, A.C. Mocuta, M. Khare, Y. Li, B. Doris, S. Shukla, T. Hughes, O. Dokumaci, S. Narasimha, S. Fung, J. Snare, B. H. Lee, J. Li, P. Ronsheim, A. Domenicucci, P. Varekamp, A. Ajmera, J. Sleight, P. O'Neil, E. Maciejewski, C. Lavoie

Year

2002

Date

2002

학회구분

International

File

2002_Tech.Dig.VLSI.Sym_H.Park.pdf (292.5K) 0회 다운로드 DATE : 2021-04-02 14:29:37