Band-Engineered Low PMOS VT with High-K/Metal Gates Featured in a Dual Channel CMOS Integration Scheme
Conference
Symp. on VLSI Tech
Author
H. Rusty Harris, P. Kalra, P M.ajhi, M. Hussain, D. Kelly, J. Oh, D. Heh, C. Smith, J. Barnett, P.D. Kirsch, G. Gebara, J. Jur, D. Lichtenwalner, A. Lubow, T.P. Ma, G. Sung, S. Thompson, B. H. Lee, H.-H. Tseng and R. Jammy
