Mechanisms Limiting EOT Scaling and Gate Leakage Currents of High-k/Metal Gate Stacks Directly on SiGe and a Method to Enable Sub-1nm EOT
Conference
Proc. Of Symp. On VLSI Technology, p.92
Author
J. Huang, P.D. Kirsch, J. Oh, S.H. Lee, J. Price, P. Majhi, H.R. Harris, D.C. Gilmer, D.Q. Kelly, P. Sivasubramani, G. Bersuker, D. Heh, C. Young, C.S. Park, Y.N. Tan, N. Goel, C. Park, P.Y. Hung, P. Lysaght, K.J. Choi, B.J. Cho, H.-H. Tseng, B.H. Lee, R.
